In order to improve the performance of BJT and HBT III-V devices, including GaAs, InP and InGaAs devices, it is desirable to lower the collector resistance. Prior art methods to decrease the collector resistance are nearing their limit. These limits are the solid solubility of dopant, especially in III-V semiconductors, and issues with thickness which cause planarization issues in the fabrication of BJT and HBT devices.
In the prior art to make low resistance contact to the intrinsic low doped collector an epitaxially grown semiconductor sub-collector layer or a series of sub-collector layers, if etch stops are required, are used. The doping concentration and thickness of these sub-collector layers are increased to lower the sub-collector resistance. However, as discussed above, there are limits to the doping concentration and thickness.
For a high performance HBT with an n-type collector, a conventional sub-collector would have an n-type doping concentration of 2*1019 cm−3, an approximate thickness of 300 nm, and be composed of InP and InGaAs layers to provide etch stops, good contact resistance, and good thermal conductivity. Doping of InP and InGaAs alloys has been demonstrated at greater than 2*1019 cm−3 levels, but these highly doped layers are only grown in the emitter of an HBT, not the collector of an HBT. A high level doping in the emitter cap layers is possible, because there are no HBT layers above the emitter in an emitter up configuration, and therefore compromising the crystal quality does not adversely affect the HBT. This trade-off cannot be made in the sub-collector where the collector, base, and emitter have yet to be grown. In addition, a 300 nm thick sub-collector could represent 30-50% of the total HBT height. The topography produced by mesa isolation can have a significant negative impact on any subsequent planarization steps during fabrication of a device.
Other prior art methods for reducing collector resistance are described in “Handbook of III-V Heterojunction Bipolar Transistors” by William Liu, Wiley-Interscience, Apr. 27, 1998. These methods of reducing the collector resistance include buried Tungsten sub-collector devices described in “Proposal of Buried metal Heterojunction Bipolar Transistor and Fabrication of HBT with Buried Tungsten” by T. Arai et al., IPRM 1999, pp. 183-186; “Tungsten buried growth by using thin flow-liner for small collector capacitance in InP HBT”, by Y. Miyamoto et al., IPRM 2005, pp. 90-93; and “CBC Reduction in GaInAs/InP buried metal heterojunction bipolar transistor”, T. Arai et al, IPRM 2000, pp. 254-257, which are incorporated herein by reference.
The disadvantages of using these prior art methods are as follows. First, materials re-growth with III-V materials is a relatively immature technology. Second, materials re-growth over a polycrystalline metal bar is required. The re-growth of InP and InGaAs alloys over such a dissimilar material compromises the material quality of the HBT. As a result, the diode characteristics, DC gain, and reliability are degraded and may not be usable in a commercial setting. Third, demonstration of these prior art technologies have only occurred at 2 μm emitter widths and the RF performance is poor (<50 GHz). This represents lower performance than the comparable GaAs SHBT (single HBT) technologies and is not competitive for high performance InP DHBTs (double HBTs). Fourth, the tungsten wires must be scaled as aggressively as the emitter width in order to ensure proper re-growth. In order to be compatible with advanced processing technology with only 250 nm wide emitters, an appropriate tungsten etch process to define 250 nm or narrower pitch lines must be developed. At present, no such process exists that is compatible with III-V device processing.
The prior art has also attempted to reduce collector resistance and solve the planarization issue by ion implanting an n-type dopant species into undoped or semi-insulating GaAs, InP, or InGaAs layers in order to create a conducting region. This conducting region is created without any topographical penalty; however, the conductivity of these implanted regions is not comparable to epitaxially grown material with equivalent thickness.
The use of 2D electron gases for High Electron Mobility Transistor (HEMT) devices is described in “Physics of Semiconductor Devices” by Simon Sze, Wiley-Interscience, 2 edition, September 1981, which is incorporated herein by reference. FIG. 1 shows the cross-section for an exemplary prior art HEMT device 10, which is a type of field effect transistor (FET). In general a FET has a source 12, a drain 14, a channel between the source 12 and the drain 14, and a gate 16 that controls the flow of electrons between the source and the drain. In a FET the channel needs to be doped with impurities to generate mobile electrons in the channel. However, the doping causes electrons to slow down because they end up colliding with the impurities which were used to generate them in the first place. In a HEMT high mobility electrons are generated in a highly-doped wide-band gap n-type donor-supply layer 18, which is shown as made of AlGaAs in FIG. 1. A low doped barrier layer 17 separates the donor-supply layer 18 from the gate. Electrons from the donor-supply layer 18 are supplied to a non-doped narrow-band gap channel layer 20 with essentially no dopant impurities, which is shown as consisting of GaAs in FIG. 1. A spacer layer 22 is between the donor supply layer 18 and the channel layer 20. The spacer layer 22 is made of the same material AlGaAs as the donor-supply layer 18; however, the spacer layer 22 has little or no doping compared to the donor-supply layer 18 in order to keep the ionized donor electrons in the channel layer 20 of GaAs. The electrons generated in the n-type AlGaAs layer drop into the GaAs layer to form a depleted AlGaAs layer, because the heterojunction created by different band-gap materials in the donor supply layer 18 and the channel layer 20 forms a quantum well in the conduction band on the channel layer 20 GaAs side from which the electrons cannot escape. Once in the channel layer 20, the electrons can move quickly without colliding with any impurities because the GaAs layer is undoped. The effect of this is to create a very thin layer of highly mobile conducting electrons with very high concentration, giving the channel layer 20 between the source and the drain very low resistivity or “high electron mobility”. This layer is called a two dimensional electron gas (2DEG).
Although a HEMT device has many useful applications, there are many other applications for which a HEMT or a FET device is not suitable. Other devices such as bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs) do not operate as FETs and do not have a channel controlled by a gate between a source and a drain. Rather a BJT has an emitter, base and collector and operates quite differently than a FET. An HBT also has an emitter, base and collector.
What is needed are lower resistance collectors in BJTs and HBTs to improve their performance. Also needed are methods for lowering the collector resistance of BJTs and HBTs. The embodiments of the present disclosure answer these and other needs.